Field of the Invention
The present invention relates to a photoelectric conversion device which outputs an output signal corresponding to a photoelectric current generated in a photoelectric conversion element.
Background Art
FIG. 4 illustrates a circuit diagram of the periphery of a photoelectric conversion element of a related art photoelectric conversion device. A circuit for the periphery of the photoelectric conversion element of the related art photoelectric conversion device is comprised of a reset circuit 103, a photodiode 105 which is the photoelectric conversion element, an NMOS transistor 415, an NMOS transistor 401, and a signal output line 403. The photodiode 105 generates a photoelectric current corresponding to the quantity of light incident thereon. The reset circuit 103 resets the voltage of the photodiode 105 to a reset voltage. The NMOS transistor 415 outputs a voltage based on the voltage of the photodiode 105 from a source thereof. The NMOS transistor 401 selects whether to output the source voltage of the NMOS transistor 415 to the signal output line 403. The reset circuit 103 is comprised of an NMOS transistor 113 having a gate connected to a reset signal input terminal 112, a drain connected to a reset voltage input terminal 120, and a source connected to an N type terminal of the photodiode 105.
The NMOS transistor 415 has a gate connected to the N type terminal of the photodiode 105, a drain connected to a power supply terminal 100, and a source connected to a drain of the NMOS transistor 401. The NMOS transistor 401 has a gate connected to an output selection signal input terminal 402 and a source connected to the signal output line 403. The photodiode 105 has a P type terminal connected to a GND terminal 101.
The related art photoelectric conversion device configured as above is operated in the following manner and outputs an output signal corresponding to the generated photoelectric current.
When a reset signal is inputted to the reset signal input terminal 112, the voltage of an N type electrode of the photodiode 105 is reset to a reset voltage Vres inputted to the reset voltage input terminal 120. Therefore, the photodiode 105 has its own parasitic capacitance charged with the reset voltage Vres. When the above reset is released, the photodiode 105 discharges the voltage of the parasitic capacitance with the photoelectric current corresponding to the incident light. After a prescribed time has elapsed, the photodiode 105 is reset again. The discharge voltage after the discharge of the photodiode 105, and the reset voltage of the re-reset photodiode 105 are respectively converted into the source voltage of the NMOS transistor 415, which is outputted to the signal output line 403 via the NMOS transistor 401 every time. The voltages based on the reset voltage and the discharge voltage of the photodiode 105 both outputted to the signal output line 403 are compared with each other by an unillustrated output circuit. The output circuit amplifies a voltage difference obtained by comparison of the voltages by means of an amplifier circuit and outputs the amplified voltage as a voltage proportional to the incident light quantity of the photodiode 105 (for example, refer to Patent Document 1).    [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-308306